PUBLICATIONS
2024
4.
Suyeon Kim; Dong Young Kim; Je Won Park; Shinwook Kim; Seungchan Lee; Han Seung Jang; Jinseok Park; Sunyong Yoo; Myoung Jin Lee
Abstract | Links | BibTeX | Dimensions | Tags: Optimization
@article{kim2024passing,
title = {Passing Word Line-Induced Subthreshold Leakage Reduction Using a Partial Insulator in a Buried Channel Array Transistor},
author = {Suyeon Kim and Dong Young Kim and Je Won Park and Shinwook Kim and Seungchan Lee and Han Seung Jang and Jinseok Park and Sunyong Yoo and Myoung Jin Lee},
url = {https://ieeexplore.ieee.org/abstract/document/10495758},
doi = {10.1109/TED.2024.3379963},
issn = {0018-9383},
year = {2024},
date = {2024-04-10},
urldate = {2024-04-10},
journal = {IEEE Transactions on Electron Devices},
volume = {71},
issue = {5},
pages = {2976 - 2982},
publisher = {IEEE},
abstract = {As dynamic random access memory (DRAM) technologies continue to be downscaled, the partial isolation type buried channel array transistor (Pi-BCAT) structure has emerged as an innovative solution for the increasing challenges caused by leakage current adjacent to passing word lines (PWLs). This study reveals that the Pi-BCAT reduces leakage currents by 30% when compared to conventional BCAT structures. Our comprehensive simulations demonstrate that Pi-BCAT is resistant to temperature-induced leakage variations, confirming its significance in promoting consistent device performance and power management. The Pi-BCAT structure is predicted to be crucial in the advancement of DRAM reliability and efficiency, hence initiating further advancements in semiconductor technology.},
note = {Correspondence to Sunyong Yoo and Myoung Jin Lee},
keywords = {Optimization},
pubstate = {published},
tppubtype = {article}
}
As dynamic random access memory (DRAM) technologies continue to be downscaled, the partial isolation type buried channel array transistor (Pi-BCAT) structure has emerged as an innovative solution for the increasing challenges caused by leakage current adjacent to passing word lines (PWLs). This study reveals that the Pi-BCAT reduces leakage currents by 30% when compared to conventional BCAT structures. Our comprehensive simulations demonstrate that Pi-BCAT is resistant to temperature-induced leakage variations, confirming its significance in promoting consistent device performance and power management. The Pi-BCAT structure is predicted to be crucial in the advancement of DRAM reliability and efficiency, hence initiating further advancements in semiconductor technology.
2022
3.
Jin Hyo Park; Su Yeon Kim; Dong Young Kim; Geon Kim; Je Won Park; Sunyong Yoo; Young-Woo Lee; Myoung Jin Lee
Abstract | Links | BibTeX | Dimensions | Tags: Optimization
@article{park2022row,
title = {Row hammer reduction using a buried insulator in a buried channel array transistor},
author = {Jin Hyo Park and Su Yeon Kim and Dong Young Kim and Geon Kim and Je Won Park and Sunyong Yoo and Young-Woo Lee and Myoung Jin Lee},
url = {https://ieeexplore.ieee.org/abstract/document/9938404},
doi = {10.1109/TED.2022.3215931},
year = {2022},
date = {2022-11-03},
urldate = {2022-11-03},
journal = {IEEE Transactions on Electron Devices},
volume = {69},
number = {12},
pages = {6710–6716},
publisher = {IEEE},
abstract = {In this article, we propose an analysis of the usage of a partial isolation type buried channel array transistor (Pi-BCAT). Compared with other structures, the conventional BCAT exhibits improved characteristics in the row hammer effect (RHE) because of its shallow drain/body (D/B) junction. Nevertheless, it remains affected by the RHE and should be mitigated because it is directly related to the reliability of dynamic random access memory (DRAM) applications. The proposed device exhibits a 50% improvement in the RHE and reduces leakage current ( IOFF ) to one-third the level of conventional BCATs while also minimizing the ON -current ( ION ) reduction. Moreover, to efficiently compare RHE, we compare ΔVSN by RHE and ΔVSN based on the gate-induced drain leakage (GIDL) according to bias conditions and the device’s parameters. Finally, we optimize the parameter values of the buried insulator by considering electrical characteristics and the RHE.},
note = {Correspondence to Myoung Jin Lee},
keywords = {Optimization},
pubstate = {published},
tppubtype = {article}
}
In this article, we propose an analysis of the usage of a partial isolation type buried channel array transistor (Pi-BCAT). Compared with other structures, the conventional BCAT exhibits improved characteristics in the row hammer effect (RHE) because of its shallow drain/body (D/B) junction. Nevertheless, it remains affected by the RHE and should be mitigated because it is directly related to the reliability of dynamic random access memory (DRAM) applications. The proposed device exhibits a 50% improvement in the RHE and reduces leakage current ( IOFF ) to one-third the level of conventional BCATs while also minimizing the ON -current ( ION ) reduction. Moreover, to efficiently compare RHE, we compare ΔVSN by RHE and ΔVSN based on the gate-induced drain leakage (GIDL) according to bias conditions and the device’s parameters. Finally, we optimize the parameter values of the buried insulator by considering electrical characteristics and the RHE.
2021
2.
Jin Hyo Park; Geon Kim; Dong Yeong Kim; Su Yeon Kim; Sunyong Yoo; Myoung Jin Lee
Abstract | Links | BibTeX | Dimensions | Tags: Optimization
@article{park2021s,
title = {S-TAT leakage current in partial isolation type saddle-FinFET (Pi-FinFET) s},
author = {Jin Hyo Park and Geon Kim and Dong Yeong Kim and Su Yeon Kim and Sunyong Yoo and Myoung Jin Lee},
url = {https://ieeexplore.ieee.org/abstract/document/9507492},
doi = {10.1109/ACCESS.2021.3102687},
year = {2021},
date = {2021-08-05},
urldate = {2021-08-05},
journal = {IEEE Access},
volume = {9},
pages = {111567–111575},
publisher = {IEEE},
abstract = {In this paper, we compare conventional saddle type FinFETs to partial isolation type saddle FinFETs (Pi-FinFETs) using 3D TCAD simulations to examine the effect of single charge traps for proper prediction of leakage current. We simulated single charge traps at various locations in the drain region, and analyzed how the traps affect leakage current. Our results show that Pi-FinFETs enhanced the leakage current characteristics given the presence of a single charge trap. Also, it was found that Pi-FinFETs exhibit half the FTAT of S-FinFETs. Based on the results from our analysis method, where we use Ioff fluctuation, the FTAT , the σF and the PF parameters to accurately compare performance, and present device design guidelines aimed at improving DRAM refresh characteristics.},
keywords = {Optimization},
pubstate = {published},
tppubtype = {article}
}
In this paper, we compare conventional saddle type FinFETs to partial isolation type saddle FinFETs (Pi-FinFETs) using 3D TCAD simulations to examine the effect of single charge traps for proper prediction of leakage current. We simulated single charge traps at various locations in the drain region, and analyzed how the traps affect leakage current. Our results show that Pi-FinFETs enhanced the leakage current characteristics given the presence of a single charge trap. Also, it was found that Pi-FinFETs exhibit half the FTAT of S-FinFETs. Based on the results from our analysis method, where we use Ioff fluctuation, the FTAT , the σF and the PF parameters to accurately compare performance, and present device design guidelines aimed at improving DRAM refresh characteristics.
1.
Zaki Masood; Hosung Park; Han Seung Jang; Sunyong Yoo; Sokhee P Jung; Yonghoon Choi
Abstract | Links | BibTeX | Dimensions | Tags: Optimization
@article{masood2020optimalc,
title = {Optimal power allocation for maximizing energy efficiency in DAS-based IoT network},
author = {Zaki Masood and Hosung Park and Han Seung Jang and Sunyong Yoo and Sokhee P Jung and Yonghoon Choi},
url = {https://ieeexplore.ieee.org/abstract/document/9166712},
doi = {10.1109/JSYST.2020.3013693},
year = {2021},
date = {2021-06-01},
urldate = {2021-06-01},
journal = {IEEE Systems Journal},
volume = {15},
number = {2},
pages = {2342–2348},
publisher = {IEEE},
abstract = {Distributed antenna system based on simultaneous wireless information and power transfer (SWIPT) can be one of the promising solutions in maximizing energy efficiency (EE), where ultra low power devices harvest energy in power splitting (PS) mode. The paradigm shift of the internet-of-things (IoT) has increased the number of IoT devices and associated sensitive data exchange on the internet. Like the EE is a noteworthy aspect in ultra low power devices, energy harvesting (EH) is an active approach from surrounding electromagnetic sources. This article deals with EE maximization for SWIPT using PS mode. In the SWIPT system, this article presents a tradeoff between EE and spectral efficiency and proposes an algorithm, which allocates optimal power to each distributed antenna port. For an IoT device, the PS scheme implements EH and information decoding operations. The proposed algorithm is based on the Lagrangian multiplier method and Karush-Kuhn-Tucker conditions to find the optimal solution without iterative computation compared to the conventional iterative method. Simulation results reveal that the proposed algorithm achieves maximum energy transfer by the using optimal PS ratio.},
keywords = {Optimization},
pubstate = {published},
tppubtype = {article}
}
Distributed antenna system based on simultaneous wireless information and power transfer (SWIPT) can be one of the promising solutions in maximizing energy efficiency (EE), where ultra low power devices harvest energy in power splitting (PS) mode. The paradigm shift of the internet-of-things (IoT) has increased the number of IoT devices and associated sensitive data exchange on the internet. Like the EE is a noteworthy aspect in ultra low power devices, energy harvesting (EH) is an active approach from surrounding electromagnetic sources. This article deals with EE maximization for SWIPT using PS mode. In the SWIPT system, this article presents a tradeoff between EE and spectral efficiency and proposes an algorithm, which allocates optimal power to each distributed antenna port. For an IoT device, the PS scheme implements EH and information decoding operations. The proposed algorithm is based on the Lagrangian multiplier method and Karush-Kuhn-Tucker conditions to find the optimal solution without iterative computation compared to the conventional iterative method. Simulation results reveal that the proposed algorithm achieves maximum energy transfer by the using optimal PS ratio.